CMOS circuit design and implementation of the discrete time chaotic chip

A discrete time chaotic signal generator has been designed and fabricated in a 0.8 μm single poly CMOS technology. The proposed chaotic circuit consists of sample-holds, opamps, a nonlinear function block and a two-phase clock generator. This paper examines numerical analysis for it´s chaotic behavior including bifurcation, Lyapunov exponent and frequency spectra. Measurement of the fabricated chaotic chip is performed with a ±2.5 V power supply and clock frequency of 10 kHz. We confirmed that a discrete time chaotic signal is generated in specific input condition. Also, we obtained diverse chaotic behavior as expected from the numerical analysis.