DocumentCode
1736342
Title
Implementation oriented theory design issues on the DTCNN template generation
Author
Brea, V.M. ; Vilariño, D.L. ; Paasio, Ari ; Cabello, D.
Author_Institution
Dept. of Electron. & Comput. Sci., Santiago de Compostela Univ., Spain
Volume
3
fYear
2002
fDate
6/24/1905 12:00:00 AM
Abstract
This paper collects all the hardware constraints considered during the system-level design phase of the so-called DTCNN pixel-level snake algorithm (PLS-algorithm). These constraints, although focused on a particular algorithm, can be taken as general guidelines aimed to achieve the lowest coefficient circuit area in DTCNN. The validity of this approach is illustrated with some data about a 9×9 DTCNN PLS-algorithm chip, which nowadays is being made in the 0.25 μm CMOS technology process provided by THOMSON.
Keywords
CMOS analogue integrated circuits; cellular neural nets; integrated circuit design; neural chips; 0.25 micron; CMOS; DTCNN template generation; PLS-algorithm; coefficient circuit area; hardware constraints; implementation oriented theory design issues; pixel-level snake algorithm; system-level design phase; Active contours; Algorithm design and analysis; CMOS technology; Cellular neural networks; Computer science; Electronic circuits; Guidelines; Hardware; Laboratories; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010170
Filename
1010170
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