Power-Aware DFT - Do we really need it?

Traditional design flows have focused on design and implementation of power mesh and on-die decoupling capacitors with an eye towards just the functional activity, average and peak, respectively. Shift speed was arbitrarily limited to reduce shift power, meet tester constraint and the constraint of shift clock being the reference clock for "on-chip PLL based scan" testing. Increased memory content (with BIST & Repair) drove the need for constraining the maximum number of memory controllers that could be run simultaneously. Power mitigation approaches like staggered BIST for memories were adopted to reduce the power supply demands on the tester.