Title :
Power-Aware DFT - Do we really need it?
Author :
Krishnamurthy, Prabhu
Author_Institution :
LSI Corp.
Abstract :
Traditional design flows have focused on design and implementation of power mesh and on-die decoupling capacitors with an eye towards just the functional activity, average and peak, respectively. Shift speed was arbitrarily limited to reduce shift power, meet tester constraint and the constraint of shift clock being the reference clock for "on-chip PLL based scan" testing. Increased memory content (with BIST & Repair) drove the need for constraining the maximum number of memory controllers that could be run simultaneously. Power mitigation approaches like staggered BIST for memories were adopted to reduce the power supply demands on the tester.
Keywords :
built-in self test; capacitors; design for testability; phase locked loops; BIST; design for testability; memory content; on-chip PLL based scan testing; on-die decoupling capacitors; power mesh; power mitigation; power-aware DFT; reference clock; shift clock; tester constraint; Automatic test pattern generation; Built-in self-test; Clocks; Delay; Energy management; Logic testing; Read-write memory; Sequential analysis; Timing; Voltage;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700659
