Toward a predictable and secure data cache algorithm: A cross-layer approach

Nowadays, the gap between processor and memory speed has grown enough to make the cache usage unavoidable in order to take real advantage of the processor´s capabilities. Nevertheless, the data cache usage causes in the same time hard real-time and security concerns. As a consequence, some real-time compliant data cache algorithms have been developed. The goal of such algorithms is to reduce the WCET (Worst-Case Execution Time) of tasks. Unfortunately they have an impact on the system security, generating breaches in the tasks partitioning. This article contributes to the definition of a data cache algorithm meeting at the same time security and real-time requirements using a cross-layering approach between the underlying hardware and the running kernel. In order to contribute to such an algorithm, this article defines properties needed at the same time by hard real-time systems and partitioned secure systems.