A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter

A 12-bit 80 Ms/s 110 mW CMOS floating analog-to-digital converter (ADC) has been integrated into an area of 0.5 mm². This ADC has excellent characteristics, such as simple architecture, small size, high speed, high resolution, low power dissipation and adaptive time sampling interval adjustment. In this design, three stages, coarse, mid and fine A/D conversion, are accomplished in floating architecture, which saves area and power dissipation. Consequently, a large number of comparators have been removed. The chip used 0.6 μm double poly, treble metal CMOS technology.