A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter

Author

Wang, Hongwei ; Chan, Cheong-Fat ; Choy, Chiu-Sing

Author_Institution

Solomon Systech Ltd., Kowloon, China

Volume

3

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

A 12-bit 80 Ms/s 110 mW CMOS floating analog-to-digital converter (ADC) has been integrated into an area of 0.5 mm². This ADC has excellent characteristics, such as simple architecture, small size, high speed, high resolution, low power dissipation and adaptive time sampling interval adjustment. In this design, three stages, coarse, mid and fine A/D conversion, are accomplished in floating architecture, which saves area and power dissipation. Consequently, a large number of comparators have been removed. The chip used 0.6 μm double poly, treble metal CMOS technology.

Keywords

CMOS integrated circuits; adaptive signal processing; analogue-digital conversion; low-power electronics; 0.6 micron; 110 mW; 12 bit; adaptive time sampling interval adjustment; area; coarse A/D conversion; double poly treble metal CMOS technology; fine A/D conversion; floating analog-to-digital converter; low power dissipation; mid A/D conversion; power dissipation; resolution; size; speed; Clocks; Decoding; Sampling methods; Signal design; Signal processing; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010179

Filename

1010179