Title :
Debug War Stories
Author_Institution :
Freescale Semicond., Austin, TX
Abstract :
Anyone that has been involved in semiconductor test has their own debug war that they have survived. It use to be that debugging customer failures would involve exchanges of code sections with the customer, timely set up of functional test patterns for containment in production and exercising the fault for failure analysis. With high fault coverage scan methodology a large part of the effort can now be achieved very efficiently using the scan-based test logic. Our approach was to utilize the customer´s functional code on a tester and make use of the scan structures of the design. For this device all clocking was supplied by the tester and the scan mode entry is via static combinational logic.
Keywords :
automatic test pattern generation; built-in self test; combinational circuits; failure analysis; fault diagnosis; integrated circuit testing; logic testing; BIST; customer return device; failure analysis; fault coverage scan methodology; functional test patterns; scan-based test logic; semiconductor test; static combinational logic; Clocks; Debugging; Failure analysis; Logic devices; Logic testing; Production; Registers; Semiconductor device testing; Shape; Software libraries;
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2008.4700672
