I/sub DDQ/ testing for submicron CMOS IC technology qualification

Author

Soden, Jerry M.

Author_Institution

Failure Anal. Dept., Sandia Nat. Labs., Albuquerque, NM, USA

fYear

1997

Firstpage

52

Lastpage

56

Abstract

Sandia is manufacturing high reliability CMOS ICs with a 0.5 micron CMP technology, as part of the progression to 0.35 micron and smaller scale technologies. To qualify this technology for delivery of high reliability ICs to customers for military, space, and commercial applications, a qualification program has been implemented that includes extensive loop testing. Two vehicles are being used for this qualification, a 256 K bit SRAM and a Microcontroller Core (MCC). Both of these ICs present unique loop testing challenges. This paper describes the methods used to successfully implement I/sub DDQ/ testing for these two types of ICs.

Keywords

CMOS digital integrated circuits; 0.5 micron; 256 Kbit; CMOS IC technology qualification; CMP technology; I/sub DDQ/ testing; SRAM chip; Sandia; high reliability CMOS ICs; loop testing; microcontroller core; qualification program; submicron CMOS ICs; CMOS integrated circuits; CMOS technology; Failure analysis; Integrated circuit testing; Isolation technology; Manufacturing; Qualifications; Random access memory; Space technology; Sputter etching;

fLanguage

English

Publisher

ieee

Conference_Titel

IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on

Conference_Location

Washington, DC, USA

Print_ISBN

0-8186-8123-3

Type

conf

DOI

10.1109/IDDQ.1997.633013

Filename

633013