Testability of path history memories with register-exchange architecture used in Viterbi-decoders

Viterbi decoders with; register-exchange path-history contain a large number of registers and multiplexers. Insertion of scan-path registers for testing purposes would generate overhead in terms of area and power-consumption. To avoid scan-registers a, methodology is presented, that allows controlling the already available multiplexers in such a way, that the registers form non-merging chains that can be included in scan-paths.