DocumentCode :
1736759
Title :
Functional test-bench refinement through automatic constraint extraction
Author :
Wang, Li.-C. ; Guzey, Onur
Author_Institution :
Univ. of California, Santa Barbara, CA
fYear :
2008
Firstpage :
1
Lastpage :
1
Abstract :
Functional verification continues to be one of the most expensive and time-consuming steps in a typical design process. Effective tests can achieve higher verification coverage in shorter time, which saves engineering resource and improve confidence on the quality of the design. However, generating effective tests for complex designs has always been a challenging problem. Instead of generating tests, the idea is to analyze the simulation trace of tests from an initial test-bench, learn from it, and extract the input constraints for controlling signals internal to the unit under test. For the experiments we used OpenSPARC T1 which is a 64-bit open-source microprocessor designed by SUN Microsystems. OpenSparc is a complex design that makes it very suitable for the experiments.
Keywords :
automatic test pattern generation; logic design; logic simulation; logic testing; microprocessor chips; OpenSPARC T1; SUN Microsystems; automatic constraint extraction; functional test-bench refinement; functional verification; open-source microprocessor; simulation trace; Analytical models; Automatic testing; Controllability; Data mining; Design engineering; Process design; Scalability; Signal analysis; Signal generators; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1089-3539
Print_ISBN :
978-1-4244-2402-3
Electronic_ISBN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2008.4700676
Filename :
4700676
Link To Document :
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