On the generation of test programs for chip multi-thread computer architectures

Within the design arena of modern devices based on cutting-edge processor cores, such as the OpenSPARC T2, the availability of effective verification, validation and test methodologies able to take advantage of high level descriptions of processor cores represents a particular advantage, since they can dramatically reduce the overall time for design and manufacturing, and improve yield and quality. A crucial role is played in this context by methods to generate effective test benches to be used for validation and test (through the software-based self-test, or SBST, paradigm). In this context, we are currently investigating innovative test set generation techniques starting from high level descriptions of processor cores that implement multi-thread architectural paradigms, such as the OpenSPARC T2 core. One of the key points of the T2 processor is the chip multi-threading and multi-core facilities, which have not been extensively considered up to now by traditional SBST strategies. The activity we will report and discuss in the panel focuses in particular on the pick stage existing in the T2 core pipeline. This module is in charge of selecting two threads out of eight for the execution and its correct behavior is essential in order to guarantee both proper functioning and maximum performance. Targeting the thread pick logic is particularly critical, since the test program requires to properly combine the execution of several threads. For example, in this case, it could be essential that every thread reaches a wait state due to all of the different wait conditions, whereas the whole test program limits the overall execution time of the thread.