Title :
Physical design automation at transistor level
Author_Institution :
Inst. de Inf. PPGC/PGMicro, Univ. Fed. do Rio Grande, Porto Alegre
Abstract :
The research and development of the design automation of integrated circuits started by the layout level and it evolved to higher levels of abstraction. At physical design level the evolution of automation was remained at the standard cell approach, where the layout of the cells are designed and included in a cell library. So, the design of the cell layout is not really automated. A cell library is also limited to small number of logic combinations. This limitation doesn´t allow reaching an optimization of the circuit at the physical design level.
Keywords :
electronic design automation; integrated circuit design; transistors; cell layout; cell library; integrated circuit design automation; layout level; logic combination; transistor level; CMOS logic circuits; Clocks; Design automation; Design optimization; Energy consumption; Integrated circuit layout; Libraries; Logic design; Minimization; Research and development;
Conference_Titel :
Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on
Conference_Location :
Tozeur
Print_ISBN :
978-1-4244-1576-2
Electronic_ISBN :
978-1-4244-1577-9
DOI :
10.1109/DTIS.2008.4540201
