DocumentCode :
1736942
Title :
Analysis of VCO jitter in chip-package co-design
Author :
Parthasarathy, H. ; Nayak, G. ; Mukund, P.R.
Author_Institution :
Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
Volume :
3
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Abstract :
Performance of a phase locked loop (PLL) is very dependent on the jitter in the voltage controlled oscillator (VCO). Traditionally, the jitter is analyzed on the basis of the nonidealities at the chip-level. In this paper, we demonstrate that package design could significantly impact jitter. Further, a novel methodology for analyzing the jitter of a VCO in a chip-package codesign methodology is presented, with the aid of an example. This methodology could easily be extended to include other sources of jitter, since there is no correlation between power supply noise and other sources. Good agreement between the theoretical prediction and simulation results is demonstrated.
Keywords :
digital phase locked loops; integrated circuit design; integrated circuit noise; jitter; phase noise; voltage-controlled oscillators; PLL; VCO; chip-package co-design; jitter; phase noise; power supply noise; simulation results; Circuit noise; Clocks; Coupling circuits; Frequency; Impedance; Jitter; Phase locked loops; Power supplies; Semiconductor device noise; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010190
Filename :
1010190
Link To Document :
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