• DocumentCode
    1736948
  • Title

    Test-Access Solutions for Three-Dimensional SOCs

  • Author

    Wu, Xiaoxia ; Chen, Yibo ; Chakrabarty, Krishnendu ; Xie, Yuan

  • Author_Institution
    Comput. Sci. & Eng. Dept., Pennsylvania State Univ., PA
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    We present a design technique for providing test access to 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The associated optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs.
  • Keywords
    integer programming; integrated circuit testing; linear programming; system-on-chip; 3D IC; 3D core-based SOC; LP-relaxation; TAM bitwidth; TSV; integer linear programming; optimization method; randomized rounding; test-access solutions; three-dimensional SOC; Benchmark testing; Circuit testing; Computer science; Design optimization; Energy consumption; Integer linear programming; Integrated circuit interconnections; Integrated circuit testing; Optimization methods; Three-dimensional integrated circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2008. ITC 2008. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-2402-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2008.4700684
  • Filename
    4700684
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1736948