• DocumentCode
    1737007
  • Title

    SoC Yield Improvement: Redundant Architectures to the Rescue?

  • Author

    Vial, J. ; Bosio, A. ; Girard, P. ; Landrault, C. ; Pravossoudovitch, S. ; Virazel, A.

  • Author_Institution
    Lab. d´´Inf., Univ. Montpellier/CNRS, Montpellier
  • fYear
    2008
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.
  • Keywords
    integrated circuit yield; redundancy; system-on-chip; SoC yield; TMR; triple modular redundancy; Automatic test pattern generation; Circuit faults; Computer architecture; Distributed computing; Fault tolerance; Logic testing; Manufacturing processes; Redundancy; Robots; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2008. ITC 2008. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-2402-3
  • Electronic_ISBN
    1089-3539
  • Type

    conf

  • DOI
    10.1109/TEST.2008.4700686
  • Filename
    4700686
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1737007