Genetic programming approach for SoC/IP floorplanning applications

This paper presents a new solution for a System on Chip/Intellectual Property (SoC/IP) module floorplanning problem using genetic programming (GP) technique. An example is demonstrated including 42 rectangular modules optimally arranged on a floorplane based on the criterion of minimized Dead Space Ratio (DSR). It is shown that the proposed approach saves considerably the calculation time as the information of each arrangement time is memorized and updated for the next time without searching or comparing data. Therefore, it can be used for a floorplanning problem with a large number of modules.