A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration

Design space exploration of new circuit methodologies require the creation of models in hardware description languages to evaluate the characteristics for different parameters, a time consuming process. To alleviate the burden of HDL construction, we present a compact netlist format and a web tool that creates syntactically correct VHDL files. The designer can use our tool, together with an easy to create netlist generator, to quickly create multiple VHDL files and skeleton test benches, to evaluate his model. Our parametrized netlist generators illustrate the efficiency of our EDA tool.