ATPG for transition faults of pipelined threshold logic circuits

Due to the recent developments in emerging switching devices the significance of threshold logic gates has drastically increased in recent years. There is an increased need to test for manufacturing defects and, in particular, for delay defects. An automatic test pattern generation approach for the transition delay fault model of pipelined current mode threshold logic circuits is introduced. This approach takes into consideration an ordering of the patterns at the input of the selected gate in order to ensure the maximum transition delay. Experimental results show the efficiency of the proposed method on selected critical gates.