Laser attacks on integrated circuits: From CMOS to FD-SOI

Author

Dutertre, J.-M. ; De Castro, S. ; Sarafianos, A. ; Boher, N. ; Rouzeyre, B. ; Lisart, M. ; Damiens, J. ; Candelier, P. ; Flottes, M.-L. ; Di Natale, G.

Author_Institution

Centre Microlectronique de Provence - Georges Charpak, ENSM.SE, Gardanne, France

fYear

2014

fDate

6-8 May 2014

Firstpage

1

Lastpage

6

Abstract

The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model permitted us to draw the laser sensitivity map of a SRAM cell. It demonstrates a very close correlation with experimental measures. We also introduce the preliminary results we gathered to build a similar electrical model for FD-SOI circuits. FD-SOI technology is expected to be less sensitive to laser than CMOS.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit modelling; laser beam effects; silicon-on-insulator; CMOS ICs; FD-SOI circuits; IC; LIESSE french national project; SRAM cell; electrical model; integrated circuits; laser attacks; laser effects; laser sensitivity map; secret data retrieval; secure integrated circuit; Integrated circuit modeling; Junctions; Laser modes; Measurement by laser beam; Photoconductivity; Semiconductor lasers; Transistors; CMOS; FD-SOI; Laser fault injection; electrical model; fault attack;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2014 9th IEEE International Conference On

Conference_Location

Santorini

Type

conf

DOI

10.1109/DTIS.2014.6850664

Filename

6850664