Layout-aware laser fault injection simulation and modeling: From physical level to gate level

Fault injection is a technique used by hackers to retrieve secret information in circuits implementing cryptographic algorithms. In particular, laser illuminations have been proven to be a very efficient mean to perform such attacks. In this paper, we present a complete laser-induced fault simulation flow geared towards the evaluation of the resistance of devices against such illuminations at design stage. For that, an accurate physical level modeling of the interaction between lasers and silicon is proposed taking into account both laser spot parameters and position and layout information. The models are abstracted at electrical and temporal/logic levels and included in a multi-level simulator.