Recent advances in single- and multi-site test optimization for DVS-based SoCs

Dynamic voltage scaling (DVS) combined with the partitioning of the System-on-Chip (SoC) into multiple voltage islands constitutes a powerful dynamic-power minimization technique. However, the sharing of the test-access mechanisms (TAMs) among different voltage islands, the necessity to test every core at multiple voltage levels and the low shift-frequency limits at the lower voltage levels introduce new test challenges and dramatically increase testing time. In this paper, we unfold challenges related to scheduling tests for DVS-based SoCs, and we describe recent advances for minimizing the test time, especially in multi-site-test environments.