Efficient error correction code configurations for quasi-nonvolatile data retention by DRAMs

This paper presents analyses of various configurations of error correction codes for the purpose of reducing the parity area for quasi-nonvolatile data retention by DRAMs. By combining long and short error correction codes, we show that the parity area can be reduced to less than 1% of the total memory size, yet the system can offer comparable reliability and adaptability as an earlier design that requires 12.5% parity area. We also claim that even without using any area for parity data, the adaptive control of the DRAM refresh rate can reduce the total risk of data loss. Finally, we discuss an efficient decoder design for long RS codes