• DocumentCode
    1738713
  • Title

    BRAINS: a BIST compiler for embedded memories

  • Author

    Cheng, Chuang ; Chih-Tsun Huang ; Huang, Chih-Tsun ; Wu, Cheng Wen ; Wey, Chen-Jong ; Tsai, Ming Chang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    299
  • Lastpage
    307
  • Abstract
    A built-in self-test (BIST) compiler for embedded memories, called BRAINS (Bist for RAm IN Seconds), is proposed. According to the memory specifications and test requirements entered by the user, BRAINS generates the synthesizable BIST code in Verilog as well as the corresponding BIST activation sequence and test-bench. The synthesis scripts for a commercial synthesis tool are also generated automatically. The architecture for the BIST circuits generated by BRAINS is an improved version of our previous design. The new design provides at-speed testing, diagnosis support, and programmable March test algorithms. The BIST compiler framework facilitates the generation of BIST circuits for various SRAM and DRAM architectures and configurations-BRAINS supports commonly used memory cores such as SRAM, EDO DRAM, SDRAM, etc. It is easy to use BRAINS for customized embedded memories. We have designed the system so that future extension to other types of memory can be done under the same framework
  • Keywords
    VLSI; application specific integrated circuits; built-in self test; circuit layout CAD; hardware description languages; high level synthesis; integrated circuit design; integrated circuit testing; integrated memory circuits; memory architecture; random-access storage; ASIC; BIST activation sequence generation; BIST compiler; BIST test-bench generation; BRAINS; DRAM architectures; SRAM architectures; SoC designs; Verilog; at-speed testing; automatic synthesis scripts generation; built-in self-test compiler; commercial synthesis tool; customized memories; diagnosis support; embedded memories; memory specifications; programmable March test algorithms; synthesizable BIST code; system-on-chip; test requirements; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Costs; Random access memory; SDRAM; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
  • Conference_Location
    Yamanashi
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-0719-0
  • Type

    conf

  • DOI
    10.1109/DFTVS.2000.887170
  • Filename
    887170