DocumentCode :
1739004
Title :
A low complex parallel decoding structure for turbo-codes
Author :
Zhongpei, Zhang ; Liang, Zhou
Author_Institution :
12th Dept., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Volume :
1
fYear :
2000
fDate :
2000
Firstpage :
312
Abstract :
The Max-Log-MAP (MLM) algorithm is simple for turbo code decoding. Based on the algorithm a parallel array structure for turbo code decoding is suggested, which is easy to implement by VLSI. In this structure, flow direction of dates and computation process of the algorithm are obtained, the relation of nodes and date frames are analyzed, and the simple time sequencing of date operation is presented. The structure is proved by simulation
Keywords :
VLSI; logic arrays; maximum likelihood decoding; turbo codes; Max-Log-MAP algorithm; VLSI; date frames; flow direction; parallel decoding structure; time sequencing; turbo codes; Algorithm design and analysis; Computational modeling; Delay; Detectors; Iterative decoding; Probability; Random access memory; Turbo codes; Very large scale integration; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication Technology Proceedings, 2000. WCC - ICCT 2000. International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-6394-9
Type :
conf
DOI :
10.1109/ICCT.2000.889220
Filename :
889220
Link To Document :
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