Title :
Low-power half-static flip-flop structure
Author :
Manolescu, Mihai ; Lin, I-Pei
Author_Institution :
Zilog Inc., Campbell, CA, USA
Abstract :
The edge triggered flip-flop is a key component of the synchronous digital design which became popular with the emerge of synthesis tools. The draw-back of this design style is the higher power consumption. This paper presents an approach which can lead to a small size, high speed flip-flop with low power requirements
Keywords :
flip-flops; high-speed integrated circuits; integrated circuit layout; integrated circuit noise; integrated logic circuits; logic design; low-power electronics; edge triggered flip-flop; half-static flip-flop structure; high speed flip-flop; low-power flip-flop structure; noise immunity; synchronous digital design; Circuit testing; Clocks; Flip-flops; Inverters; Libraries; Logic; Master-slave; Power dissipation; Power supplies; Voltage;
Conference_Titel :
Semiconductor Conference, 2000. CAS 2000 Proceedings. International
Conference_Location :
Sinaia
Print_ISBN :
0-7803-5885-6
DOI :
10.1109/SMICND.2000.890220
