DocumentCode :
1739404
Title :
Analysis and improvement of high-speed SDH frame alignment
Author :
Yanping, Sha ; Hansheng, Wang ; Lieguang, Zeng
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Volume :
2
fYear :
2000
fDate :
2000
Firstpage :
1024
Abstract :
The frame aligner is a key part in a digital multiplexer/demultiplexer system. A novel error tolerant frame alignment methodology is presented in this paper. Analysis shows that this method complies with ITU-T recommendation and improves the performance. The parameters of frame aligner and framing pattern are carefully selected. Finally, the parallel realization of a frame aligner with the proposed method, which can lower the working frequency and power, is applied in an STM-4 system
Keywords :
demultiplexing; synchronous digital hierarchy; ITU-T recommendation; STM-4 system; digital demultiplexer; digital multiplexer; framing pattern; high-speed SDH frame alignment; synchronous digital hierarchy; Artificial intelligence; Frequency; Multiplexing; Performance analysis; Performance evaluation; Phase detection; Protection; Synchronous digital hierarchy; Time measurement; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication Technology Proceedings, 2000. WCC - ICCT 2000. International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-6394-9
Type :
conf
DOI :
10.1109/ICCT.2000.890850
Filename :
890850
Link To Document :
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