A system level integration design for MPEG layer III audio decoder

Author

Tsai, Tsung-Han

Author_Institution

Dept. of Electron. Eng., Fu Jen Univ., Taiwan, China

Volume

2

fYear

2000

fDate

2000

Firstpage

1333

Abstract

MPEG Layer III audio decoding algorithms are involved in several complex-coding techniques and therefore it is difficult to design efficient dedicated architecture. We present a semi-ASIC architecture for an MPEG Layer III audio decoder. The MPEG Layer III algorithms can be divided into two types of operations. With an embedded RISC core and the two dedicated processing units, each type of operation can be performed efficiently. The decoder is designed based on the approaches of simplicity and low cost while meeting the high-efficiency requirements

Keywords

application specific integrated circuits; audio coding; code standards; data compression; decoding; pipeline processing; reduced instruction set computing; telecommunication standards; MPEG layer III audio decoder; audio decoding algorithms; dedicated architecture; dedicated processing units; digital audio broadcasting; digital audio coding; embedded RISC core; high-efficiency decoder; low cost decoder; pipeline processing; semi-ASIC architecture; system level integration design; Algorithm design and analysis; Audio coding; Audio compression; Computer architecture; Costs; Decision making; Decoding; Frequency; Hardware; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Proceedings, 2000. WCCC-ICSP 2000. 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-5747-7

Type

conf

DOI

10.1109/ICOSP.2000.891792

Filename

891792