DocumentCode
1739703
Title
An advanced input-queued ATM switch with a pipelined approach to arbitration
Author
Jeong, Gab Joong ; Lee, Bhum Cheol ; Bhum Cheol Lee
Author_Institution
Switching Tech. Dept., ETRI, Taejon, South Korea
Volume
1
fYear
2000
fDate
2000
Firstpage
496
Abstract
In this paper, we consider the transmission latency of request and grant data between input buffers and a central arbiter in an input-queued ATM switch. We propose a new input queuing switch architecture to allow the transmission latency and to increase the throughput of a switching system using a pipelined approach to ATM switch arbitration. Our scheme achieves the same saturation throughput as an output-queued ATM switch, using the arbitration algorithm of a basic 2DRR
Keywords
asynchronous transfer mode; buffer storage; pipeline processing; queueing theory; ATM switch; arbitration algorithm; central arbiter; grant data; input buffers; input queuing switch architecture; pipelined approach; request data; saturation throughput; transmission latency; Aggregates; Asynchronous transfer mode; Communication switching; Data communication; Delay; Logic design; Radio frequency; Switches; Switching systems; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Global Telecommunications Conference, 2000. GLOBECOM '00. IEEE
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-6451-1
Type
conf
DOI
10.1109/GLOCOM.2000.892053
Filename
892053
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