Preparation of 200 mm silicon substrates with metal ground-plane for double-gate SOI devices

As the current CMOS VLSI technology approaching fundamental limits in the deep submicron regime, double-gate SOI devices provide an alternative device structure to further extend the device scaling approach (Wong et al, 1997; Wong et al, 1998; Huang et al, 1999). Furthermore, the replacement of traditional poly Si gate with proper metal gate materials such as tungsten is a promising approach to improve the conductance of the gate electrode and to eliminate the depletion in the poly-Si gate (Buchanan et al, 1998). However, the compatibility of metal materials with current Si VLSI technology remains a challenge. In this work, new processes have been developed to incorporate mid-gap metal tungsten in SOI substrates. 200 mm SOI substrates with buried tungsten ground-plane have been fabricated for the purpose of fabricating double-gate SOI devices with metal back-gate