Title :
Parallel algorithms for detecting hazards in combinational logic circuits
Author_Institution :
Sch. of Comput. Eng., Nanyang Technol. Inst., Singapore
Abstract :
Data and control parallelism algorithms are described for a matrix method which detects and locates the presence of logic hazards in combinational logic circuits. Examples are given for illustration
Keywords :
combinational circuits; hazards and race conditions; matrix algebra; parallel algorithms; combinational logic circuits; control parallelism algorithms; data parallel algorithms; hazards detection; logic hazards; matrix method; Circuit analysis; Circuit testing; Combinational circuits; Hazards; Input variables; Logic; Parallel algorithms; Parallel processing; Propagation delay; Pulse circuits;
Conference_Titel :
TENCON 2000. Proceedings
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7803-6355-8
DOI :
10.1109/TENCON.2000.893565
