Author :
Hayat, F. ; Williams, T.W. ; Kapur, R. ; Hsu, D.
Author_Institution :
Synopsis Inc., Mountain View, CA, USA
Abstract :
It is becoming evident that testability must be addressed throughout the entire design process. To successfully meet all the design goals of today´s and tomorrow´s enormously complex devices, swift convergence of function, timing, area and power requirements must be simultaneously accompanied by new test tools that enable rapid, predictable and repeatable DFT closure. Achieving successful DFT closure requires that RTL designers and DFT engineers work in concert on a unified view of the design, using integrated tools and flows. It also requires that DFT tools have zero impact on critically important timing closure flows
Keywords :
application specific integrated circuits; automatic testing; design for testability; integrated circuit testing; logic testing; ASIC; SoC; area requirement; power requirement; testability; timing closure flow; Application specific integrated circuits; Design engineering; Design for testability; Design methodology; Electronic design automation and methodology; Electronic equipment testing; Life testing; Manufacturing; Process design; Timing;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893592
