Title :
Testing programmable interconnect systems: an algorithmic approach
Author :
Liu, B. ; Lombardi, F. ; Huang, W.-K.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
Presents an approach for fault detection in programmable wiring networks (PWNs). A comprehensive fault model which includes faults in the nets (open, stuck-at and shorts) as well as in the switches (stuck-off, stuck-on and programming faults) is assumed at both the physical and behavioral levels. In a PWN, the most important issue is to find the minimal number of configurations (or programming phases) as the dominant figure of merit of testing. Through the construction of different graphs, it is shown that this process corresponds to finding the node-disjoint path-sets such that each switch is turned on/off at least once and adjacencies in the nets for possible bridge faults (shorts) are verified. To account for 100% fault coverage of bridge faults, a post-processing algorithm may be required
Keywords :
automatic test software; circuit analysis computing; circuit testing; fault diagnosis; interconnected systems; interconnections; programmable circuits; algorithmic approach; bridge faults; comprehensive fault model; fault coverage; fault detection; figure of merit; graphs; minimal configuration number; network adjacencies; network faults; node-disjoint path-sets; open faults; post-processing algorithm; programmable interconnect systems testing; programmable wiring networks; programming faults; programming phases; short circuits; stuck-at faults; stuck-off faults; stuck-on faults; switch faults; switching; Bridge circuits; Circuit faults; Computer science; Integrated circuit interconnections; Joining processes; Pins; Switches; Switching circuits; System testing; Wiring;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893642
