Title :
The SIMD architecture for the post-stage tasks of motion estimation
Author :
Wujian, Zhang ; Xiaohai, Qiu ; Runde, Zhou ; Hongyi, Chen ; Toshio, Kondo ; Takayosh, Nakashima ; Tsunehachi, Ishitani
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A new architecture using only a single module to implement the post stage tasks of motion estimation is proposed, which has a single instruction stream over multiple data streams (SIMD). Under the control of a simple RISC-like core, an improved tree array concurrently executes vector instructions. A block memory scheme and an evenly time sharing accessing method simplify the management of the on chip data memory and also reduce the memory capacity. A circuit based on this architecture has been integrated by NEL Corporation (NTT Electronics, Japan) into the single MPEG-2 MP@ML encoder chip using 0.25 μm CMOS technology
Keywords :
CMOS digital integrated circuits; digital signal processing chips; motion estimation; parallel architectures; reduced instruction set computing; video coding; 0.25 micron; CMOS technology; MPEG-2 video encoder chip; NEL Corporation; NTT Electronics; RISC-like core; SIMD architecture; block memory scheme; memory capacity reduction; motion estimation; multiple data streams; post-stage tasks; single instruction stream; time sharing accessing method; tree array; vector instructions execution; Bidirectional control; CMOS technology; Encoding; Hardware; Integrated circuit technology; Memory management; Motion estimation; Power dissipation; Transform coding; Video compression;
Conference_Titel :
Signal Processing Proceedings, 2000. WCCC-ICSP 2000. 5th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-5747-7
DOI :
10.1109/ICOSP.2000.894569
