Detailed analysis of enhancement-mode technologies for the development of high performance, power conserving, mixed-signal integrated circuits

An important aspect in developing digital receivers is the reduction of analog components, which tend to be temperature sensitive and require calibration and result in a reduction in receiver accuracy. Digital receivers are a long-term goal of the Air Force, which strive for increased functionality interactive capability amongst air, space and ground based platforms. Therefore, in the proper designing of that digital receiver an intricate tradespace exists in order to maintain the power performance relationship needed to meet platform requirements, and reducing acquisition and lifecycle costs. This paper summarizes efforts to completely analyze two complementary enhancement-mode technologies, GaAs CHFET and SOI CMOS, which could be implemented at the front end of the digital receiver and result in an appropriate power/performance improvement. This effort begins with a detailed radio frequency (RF) characterization of each technology, the building of a complete RF model, and the correct choice of enhancement-mode, high performance mixed-signal circuit designs. This type of ground level approach is critical to any future digital receiver architecture where platform power budget constraints must be met, while producing the maximum performance