Title :
Tradeoffs in modeling the response of power delivery systems of high-performance microprocessors
Author :
Beker, Benjamin ; Hirsch, Tom
Author_Institution :
Adv. Micro Devices Inc., Austin, TX, USA
Abstract :
This paper discusses some tradeoffs associated with building a partial element equivalent circuit (PEEC)-based distributed circuit model for the power delivery systems of high-speed microprocessors packaged in a ceramic pin grid array (CPGA) form factor. The main focus of the paper is on how specific simplification of the model geometry affects the accuracy of the results. Moreover, the tradeoffs between speed and accuracy associated with the additional approximations to the numerical methods used to extract the equivalent circuit parameters are also discussed. Finally, numerical results for the microprocessor disturbances on the power system of typical CPGA packages are presented
Keywords :
ceramic packaging; equivalent circuits; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit packaging; microprocessor chips; numerical analysis; power supply circuits; CPGA form factor; CPGA packages; PEEC-based distributed circuit model; ceramic pin grid array form factor; equivalent circuit parameters; high-performance microprocessors; high-speed microprocessors; microprocessor disturbances; model accuracy; model geometry simplification; model speed/accuracy trade-offs; modeling trade-offs; numerical methods; partial element equivalent circuit-based distributed circuit model; power delivery system response; power delivery systems; power system; Capacitance; Equivalent circuits; Geometry; Inductance; Microprocessors; Packaging; Power system modeling; Power system simulation; Resonance; Solid modeling;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-6450-3
DOI :
10.1109/EPEP.2000.895497
