Contact-pad design for high-frequency silicon measurements

Author

Williams, Dylan F. ; Byers, Andrew C. ; Tyre, Vance C. ; Walker, David K. ; Ou, Jeffrey J. ; Jin, Xiaodong ; Piket-May, Melinda ; Hu, Chenming

Author_Institution

Nat. Inst. of Stand. & Technol., Boulder, CO, USA

fYear

2000

fDate

2000

Firstpage

131

Lastpage

134

Abstract

We measure and compare the electrical parasitics of contact pads of different designs fabricated on silicon integrated circuits and develop a strategy for reducing the parasitics. We used an on-wafer probe system calibrated with the multiline through-reflect-line (TRL) probe-tip calibration

Keywords

calibration; electrical contacts; elemental semiconductors; integrated circuit interconnections; integrated circuit measurement; integrated circuit noise; integrated circuit packaging; probes; silicon; Si; contact pad; contact pad design; contact-pad design; electrical parasitics; high-frequency silicon measurements; multiline TRL probe-tip calibration; multiline through-reflect-line probe-tip calibration; on-wafer probe system; parasitics reduction; silicon integrated circuits; Calibration; Capacitance measurement; Contacts; Coplanar waveguides; Electric variables measurement; Integrated circuit measurements; Microstrip; Parasitic capacitance; Signal design; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2000, IEEE Conference on.

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-6450-3

Type

conf

DOI

10.1109/EPEP.2000.895510

Filename

895510