Design of 3.3 V 10 bit current-mode folding/interpolating CMOS A/D converter with an arithmetic functionality

Author

Chung, Jin Won ; Yoon, Kwang Sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

fYear

2000

fDate

2000

Firstpage

45

Lastpage

48

Abstract

A low power 10 bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent the ADC from increasing the FR excessively, but also to perform at high resolution with a single power supply of 3.3 V. The proposed ADC is implemented by a 0.6 μm n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ±0.5 LSB, an integral nonlinearity (INL) of ±1.0 LSB

Keywords

CMOS integrated circuits; analogue-digital conversion; current-mode circuits; digital arithmetic; high-speed integrated circuits; integrated circuit design; interpolation; low-power electronics; 0.6 micron; 10 bit; 3.3 V; CMOS A/D converter; analog to digital converter; arithmetic functionality; current-mode ADC; current-mode two-level folding amplifier; differential nonlinearity; folding/interpolating ADC; high resolution; integral nonlinearity; low power operation; n-well CMOS process; single poly/double metal process; single power supply; Analog-digital conversion; CMOS process; CMOS technology; Current mode circuits; Digital arithmetic; Digital signal processing chips; Frequency; Power dissipation; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896904

Filename

896904