A 2 V clock synchronizer using digital delay-locked loop

Author

Hwang, Chomg-Sii ; Chung, Wang-Chih ; Wang, Chih-Yong ; Tsao, Hen-Wai ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2000

fDate

2000

Firstpage

91

Lastpage

94

Abstract

A 2 V clock synchronizer chip using digital delay-locked loop is presented. It is targeted to provide synchronous clock distribution in high-speed digital systems. A simple structure with a counter-based delay line is used for compensating the skew caused by process, voltage, temperature and length. A stability criterion is also obtained. Experimental results have demonstrated its advantages like good stability, wide tuning range and low power consumption

Keywords

circuit stability; circuit tuning; clocks; delay lines; delay lock loops; high-speed integrated circuits; low-power electronics; synchronisation; clock synchronizer chip; counter delay line; digital delay locked loop; high-speed digital system; low-power circuit; skew compensation; stability; tuning range; Clocks; Counting circuits; Delay lines; Feedback; Frequency synchronization; Phase detection; Phase locked loops; Propagation delay; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896916

Filename

896916