Designing built-in self-test circuits for embedded memories test

This paper describes practical issues on designing and implementing industrial built-in self-test circuits for embedded memory test. The proposed test circuits are power conscious, fault locatable, and scan-based-test friendly. These features are notable and useful practically in system-on-a-chip design test because many memories that are repairable and large-sized are commonly embedded in the design. We applied the proposed test circuits to actual RAMs available in industry. Experimental results show that the test circuits are powerful for the RAM test with small penalties of area, delay, and power consumption, compared with no use of the test circuit. Furthermore, the test circuits improve the scan-based testability for the glue logic surrounding the RAMs