A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)

Author

Eto, Satoshi ; Akita, Hironobu ; Isobe, Katsuaki ; Tsuchida, Kenji ; Toda, Hiroaki ; Seki, Teruo

Author_Institution

Fujitsu Labs. Ltd., Japan

fYear

2000

fDate

2000

Firstpage

349

Lastpage

350

Abstract

A new Delay Locked Loop (DLL) using a Digital-to-Analog Converter with the Parallel Variable Resister (PVR-DAC) has been developed. The PVR-DAC successfully manages the current controlled-delay element (CCDE) and achieves a fine time-based resolution. The DLL adopting PVR-DAC has been simulated. It realizes a time-based resolution of 18 ps, an operation frequency range of 143 MHz through 333 MHz, with the maximum power consumption of 20 mW at 1.5 V, and also achieves the small circuit area of 0.5 mm²

Keywords

CMOS digital integrated circuits; circuit feedback; delay lines; delay lock loops; digital-analogue conversion; 1.5 V; 143 to 333 MHz; 18 ps; 20 mW; circuit area; current controlled-delay element; current-controlled delay; digital DLL; fine time-based resolution; maximum power consumption; operation frequency range; parallel variable resistor DAC; time-based resolution; CMOS technology; Counting circuits; Delay lines; Energy consumption; Energy management; Equations; Frequency; MOS devices; Resistors; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Conference_Location

Cheju

Print_ISBN

0-7803-6470-8

Type

conf

DOI

10.1109/APASIC.2000.896980

Filename

896980