DocumentCode :
174123
Title :
A high-resolution analog-to-digital converter design for sub-100 nm technology using folding-integration technique
Author :
Amin, Khandaker Mohammad Raisul ; Kawahito, S.
Author_Institution :
Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan
fYear :
2014
fDate :
23-24 May 2014
Firstpage :
1
Lastpage :
5
Abstract :
To design a low-power, high-speed and high-resolution analog-to-digital converter (ADC) in sub-100 nm technology, this paper presents a technique using folding integration (F. I.) and digital calibration. We have compared the circuit simulation results with the ideal case (Matlab simulation results) and have done nonlinearity analysis. The effectiveness of the digital error correction is confirmed by simulations.
Keywords :
analogue-digital conversion; calibration; error correction; ADC; Matlab simulation; circuit simulation; digital calibration; digital error correction; folding-integration technique; high-resolution analog-to-digital converter design; nonlinearity analysis; size 100 nm; Analog-digital conversion; Calibration; Capacitors; Circuit simulation; DH-HEMTs; Error correction; Informatics; Folding integration ADC; digital calibration; high resolution; multiple sampling technique; signal-to-noise ratio(SNR);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Informatics, Electronics & Vision (ICIEV), 2014 International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4799-5179-6
Type :
conf
DOI :
10.1109/ICIEV.2014.6850811
Filename :
6850811
Link To Document :
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