DocumentCode :
174129
Title :
Hardware architecture design of Anemia detecting regression model based on FPGA
Author :
Khan, Muhammad Imran ; Mondol, Raktim Kumar ; Zamee, Muhammad Ahsan ; Tarique, Tanvir Ahmad
Author_Institution :
Dept. of EEE, World Univ. of Bangladesh, Dhaka, Bangladesh
fYear :
2014
fDate :
23-24 May 2014
Firstpage :
1
Lastpage :
5
Abstract :
This paper proposes Field Programmable Gate Array (FPGA) based architecture for simple, portable, low cost anemia detector by implementing in verilog HDL. Noninvasive diagnosis of anemia shows that color of blood can give an indication to the severity of Anemia. Moreover simplicity of this computational image processing method makes it essential to implement it in hardware level. Because of using floating point algorithm same result is found after simulation in matlab and Verilog. By using this system patients can easily check his hemoglobin level of blood.
Keywords :
blood; computer vision; field programmable gate arrays; floating point arithmetic; hardware description languages; image colour analysis; logic design; medical image processing; proteins; regression analysis; FPGA; Matlab; Verilog HDL; anemia detecting regression model; blood color; computational image processing method; field programmable gate array based architecture; floating point algorithm; hardware architecture design; hemoglobin level; noninvasive anemia diagnosis; Blood; Clocks; Hardware design languages; Image color analysis; Mathematical model; Radiation detectors; Random access memory; Anemia; FPGA; Floating point algorithm Hemoglobin; Verilog HDL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Informatics, Electronics & Vision (ICIEV), 2014 International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4799-5179-6
Type :
conf
DOI :
10.1109/ICIEV.2014.6850814
Filename :
6850814
Link To Document :
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