DocumentCode
1742483
Title
Recent advances in underfill technology for flip-chip, ball grid array, and chip scale package applications
Author
Wang, Lejun ; Wong, C.P.
Author_Institution
Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2000
fDate
2000
Firstpage
224
Lastpage
231
Abstract
With the paradigm shift of microelectronic packages to low cost, miniaturization, high performance, and high reliability, area array interconnecting technologies including flip-chip, ball grid array, and chip scale packages are becoming the mainstream technologies to package IC chips for cheaper, smaller, lighter, yet higher performance electronic devices. Underfill technology is critical to the reliability of area array technologies, and thus is very important to the electronics packaging industry. This paper gives an overview of the evolution of underfill technology, focusing on its recent advances, including new underfilling processes and the new types of underfills that are involved. These include reworkable underfills, no-flow underfills, molded underfills, and wafer-level-applied underfills. In this paper, different types of reworkable underfill formulations and the methodologies for their development are compared. Furthermore, generic concepts of the new underfilling processes, including no-flow, molding, wafer-level, and the underfills involved in each process, are introduced
Keywords
ball grid arrays; chip scale packaging; encapsulation; flip-chip devices; integrated circuit interconnections; integrated circuit reliability; microassembling; moulding; plastic packaging; reviews; IC chips; area array interconnecting technologies; area array technologies; ball grid array; ball grid array package; chip scale package; electronic devices; electronics packaging; flip-chip package; microelectronic packages; miniaturization; molded underfills; no-flow underfills; package cost; package performance; package reliability; reliability; reworkable underfill formulations; reworkable underfills; underfill technology; underfilling processes; underfills; wafer-level-applied underfills; Ceramics; Chip scale packaging; Copper; Costs; Electronics packaging; Integrated circuit packaging; Lead; Materials science and technology; Silicon; Surface-mount technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Materials and Packaging, 2000. (EMAP 2000). International Symposium on
Conference_Location
Hong Kong
Print_ISBN
0-7803-6654-9
Type
conf
DOI
10.1109/EMAP.2000.904159
Filename
904159
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