A design and manufacturing solution for high reliable non-leaded CSP´s like QFN

The ongoing miniaturization and increasing functionality of electronic equipment have forced the semiconductor industry to develop smaller and thinner devices in ever-shorter cycles. The trend for chip scale area/perimeter array packages is obvious. One of these extremely miniaturized IC packages, presented by Matsushita under the name QFN, has rapidly become popular. However, one concern is the limited device reliability (JEDEC moisture level 3) which requires improvements for main markets such as telecommunication and automotive electronics. Rapidly implemented miniaturization in the past has led to reduced device reliability, e.g. for the well-known “popcorn phenomenon”, from which most thin devices like PBGAs, TQFPs, TSOPs, etc., suffer. In addition, increasing time to market pressure forces the industry to shorten package design time. Under this pressure, the complexity and link between package manufacturability and device reliability is sometimes neglected. The resulting dissatisfaction has initiated a design and manufacturing process research program, targeting best board assembly quality and a reliability performance level of at least JEDEC-moisture level 1. By carefully analyzing all constraints which limit device and board assembly quality of such new devices using all past experiences and by considering the capabilities of existing and established assembly and packaging technologies, it should be possible to build and economically manufacture such devices in high volume, achieving the required board assembly quality and device reliability in the requested cost frame