DocumentCode :
1742518
Title :
A versatile 0.13 /spl mu/m CMOS platform technology supporting high performance and low power applications
Author :
Perera, A.H. ; Smith, Brian ; Cave, N. ; Sureddin, M. ; Chheda, Sonam ; Islam, Rashed ; Chang, Joana ; Song, S.-C. ; Sultan, Ahmed ; Crown, S. ; Kolagunta, V. ; Shah, Shalin ; Celik, M. ; Wu, Dalei ; Yu, K.C. ; Fox, R. ; Park, Soojin ; Simpson, Cheslan ;
Author_Institution :
Digital DNA Labs., Motorola Inc., Austin, TX, USA
fYear :
2000
fDate :
10-13 Dec. 2000
Firstpage :
571
Lastpage :
574
Abstract :
A modular 0.13 /spl mu/m CMOS platform has been developed to support a wide range of applications, including embedded non-volatile memory (NVM). The high performance core device with a 18 /spl Aring/ gate oxide supports the high end needs of the technology. In addition, medium performance and low leakage 25 /spl Aring/ devices are provided in the technology platform to service the low power applications, with low off-state leakage. The peripheral I/O devices support both 2.5 V (50 /spl Aring/) and 3.3 V (70 /spl Aring/) interfaces. Gate lengths range from 110 to 80 nm. Optical enhancement techniques allow use of 248 nm KrF lithography to meet the patterning needs. The interconnect technology allows for two low-k dielectric options with K-values in the range from 2.9 to 3.6. Aggressive design rules, fully compatible with 248 nm KrF systems allow for high logic densities and a 2.48 um/sup 2/ 6T embedded SRAM cell. The technology has been exercised using a 4MB SRAM test vehicle with good yields.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit interconnections; low-power electronics; ultraviolet lithography; 0.13 micron; 2.5 V; 248 nm; 3.3 V; 4 MB; CMOS modular platform technology; DUV lithography; I/O device; SRAM cell; embedded nonvolatile memory; gate oxide; interconnect technology; low-k dielectric; low-power design; off-state leakage; optical enhancement technique; CMOS technology; Dielectrics; Lithography; Logic design; Nonvolatile memory; Optical interconnections; Power system interconnection; Random access memory; Testing; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
Type :
conf
DOI :
10.1109/IEDM.2000.904384
Filename :
904384
Link To Document :
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