Title :
A novel area-efficient binary adder
Author :
Furber, S.B. ; Liu, J.
Author_Institution :
Dept. of Comput. Sci., Univ. of Manchester, UK
fDate :
Oct. 29 2000-Nov. 1 2000
Abstract :
A novel circuit for binary addition based on a parallel-prefix carry structure is presented. This circuit uses a recoding of the conventional carry kill and generate terms to yield a number of improvements over previous designs. In particular, a single circuit produces both the carry signals and the Sum Sum+1 data that is required for a carry selection circuit, supporting a range of possible implementations all of which have high performance, regular layout and good area-efficiency. the simple design also leads to good power-efficiency. Binary adders based on this technique have been used in the ARM9TDMI, the ARM Piccolo DSP coprocessor, and AMULET3 asynchronous ARM processor.
Keywords :
adders; coprocessors; digital signal processing chips; integrated circuit design; AMULET3 asynchronous ARM processor; ARM Piccolo DSP coprocessor; ARM9TDMI; area-efficiency; area-efficient binary adder; binary addition; carry selection circuit; carry signals; high performance; parallel-prefix carry structure; power-efficiency; recoding; regular layout; Adders; Boolean functions; CMOS logic circuits; Computer science; Delay; Energy consumption; Equations; Input variables; Sequential circuits; Signal generators;
Conference_Titel :
Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-6514-3
DOI :
10.1109/ACSSC.2000.910928
