Implementation of canonical and retimed RNS architectures for the orthogonal 1-D DWT over FPL devices

Author

Ramirez, J. ; García, A. ; Fernández, P.G. ; Parrilla, L. ; Lloris, A.

Author_Institution

Dept. of Electron. & Comput. Technol., Granada Univ., Spain

Volume

1

fYear

2000

fDate

Oct. 29 2000-Nov. 1 2000

Firstpage

384

Abstract

This paper shows the design and implementation of canonical and retimed RNS (Residue Number System) architectures for the direct and inverse orthogonal Discrete Wavelet Transform (DWT). They allow sharing of the low-pass filter Look-Up Tables (LUTs) to compute the two filter bank outputs. These architectures enable the use of fine-grain pipelining in the modular adder trees, the use of only one adder tree and the redistribution of module multiplier LUTs. Their implementation on Field-Programmable Logic (FPL) devices was carried out to compare both solutions with binary 2´s complement arithmetic solutions.

Keywords

adders; discrete wavelet transforms; field programmable gate arrays; integrated circuit design; pipeline arithmetic; residue number systems; table lookup; canonical RNS architectures; field-programmable logic devices; filter bank outputs; fine-grain pipelining; low-pass filter look-up tables; modular adder trees; module multiplier LUTs; orthogonal 1D DWT; retimed RNS architectures; Arithmetic; Computer architecture; Digital signal processing; Discrete wavelet transforms; Filter bank; Logic devices; Propagation delay; Random access memory; Table lookup; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-6514-3

Type

conf

DOI

10.1109/ACSSC.2000.910983

Filename

910983