• DocumentCode
    1743331
  • Title

    FIR filter mapping and performance analysis on MorphoSys

  • Author

    Diab, Hassan ; Abdennour, Emad ; Kurdahi, Fadi

  • Author_Institution
    Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
  • Volume
    1
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    99
  • Abstract
    This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) from UCI. A mapping of the FIR filter algorithm onto this hardware is proposed. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the FIR execution on the M1 system. An example (8-tap FIR filter on an 8×8 RC array M1) was run, to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operation
  • Keywords
    FIR filters; application specific integrated circuits; digital filters; reconfigurable architectures; FIR execution; FIR filter mapping; MorphoSys; mULATE program; performance analysis; reconfigurable computing; Broadcasting; Computer architecture; Concurrent computing; Design engineering; Finite impulse response filter; Hardware; Performance analysis; Process control; Prototypes; Radio control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
  • Conference_Location
    Jounieh
  • Print_ISBN
    0-7803-6542-9
  • Type

    conf

  • DOI
    10.1109/ICECS.2000.911494
  • Filename
    911494
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1743331