A two-step quantization ΔΣ-modulator architecture with cascaded digital noise cancellation

The quantization in a multi-bit ΔΣ-modulator feedback loop can be divided into two time steps, thus reducing the analog hardware complexity. As extra delay in the feedback path would lead to instability, a partial conversion result with reduced resolution of N bits is fed back immediately and a corrective term with full resolution of N+M bits is fed back one clock cycle later. The effective resolution corresponds to N+M bits at low frequencies, but at high frequencies, the feedback is unable to suppress the coarse quantization made during the first step. It is shown, in this paper, that the coarse quantization error can be altogether removed in digital domain by using information in the corrective feedback term. The basic principle is the same as in cascaded ΔΣ-modulators, but the digital cancellation has to comply with the coarse error transfer function, which is different from that of the analog loop. Furthermore, the proposed architecture is shown to be inherently insensitive to nonidealities in the analog noise shaping loop, which is a well known problem with cascade ΔΣ-modulators