Title :
Delay oriented design methodology: application to the design of a VHF low power VLSI polyphase oscillator
Author :
Spataro, A. ; Deval, Y. ; Bégueret, J.B. ; Fouillat, P.
Author_Institution :
Lab. IXL, Talence, France
Abstract :
A new design methodology (Delay Oriented Design-DOD) has been developed in order to design a novel oscillator architecture. A 250 MHz DOD oscillator has been implemented on a 0.8 μm, two metal layers standard VLSI CMOS technology. It provides both in-phase and quadrature-phase differential outputs on a 60 MHz frequency range. The measured phase noise at 1 kHz offset from the carrier is about -92 dBc/Hz. The oscillator current consumption is 3 mA on a 3.3 V voltage supply
Keywords :
CMOS integrated circuits; VHF oscillators; VLSI; delay lock loops; integrated circuit design; low-power electronics; 0.8 micron; 250 MHz; 3 mA; 3.3 V; DLL; VHF low power oscillator; VLSI polyphase oscillator; delay oriented design methodology; in-phase differential outputs; oscillator architecture; quadrature-phase differential outputs; two metal layer CMOS technology; CMOS technology; Current measurement; Delay; Design methodology; Frequency; Noise measurement; Oscillators; Phase measurement; US Department of Defense; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911530
