Title :
Design of novel macro-cells for next generation ASIC cell library
Author :
Cho, Kiseon ; Song, Minkyu
Author_Institution :
Dept. of Semicond. Sci., Dongguk Univ., Seoul, South Korea
Abstract :
This paper describes a design methodology of novel macro-cells for next generation ASIC libraries that has a low-power consumption and high-speed operation. In order to satisfy the desired characteristics, novel architectures of adder, multiplier, and shifter are proposed. Further, automatic layout generation programs are proposed. They are designed on the basis of the standard-cell approach and they generate the layouts of the proposed macro-cells from 8-bit to 64-bit. The proposed macro-cells are designed with a novel compound logic that consists of both CMOS logic and pass-transistor logic. They are fabricated with 0.25 μm 1-poly 5-metal CMOS process, and have desired experimental results
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; application specific integrated circuits; circuit CAD; circuit layout CAD; high-speed integrated circuits; integrated circuit design; logic CAD; low-power electronics; 0.25 micron; 1-poly 5-metal CMOS process; 8 to 64 bit; CMOS logic; PTL; adder architecture; automatic layout generation programs; barrel shifter architecture; design methodology; high-speed operation; low-power consumption; macro-cell design; multiplier architecture; next generation ASIC cell library; pass-transistor logic; standard-cell approach; Application specific integrated circuits; Automatic logic units; CMOS logic circuits; CMOS process; Data processing; Decoding; Design methodology; Electronic mail; Libraries; Logic design;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911546
